In the integrated circuit industry today, hundreds of thousands of semiconductor devices are built on a single chip. Every device on the chip must be electrically isolated to ensure that it operates independently without interfering with another. The art of isolating semiconductor devices has become an important aspect of modern metal-oxide-semiconductor (MOS) and bipolar integrated circuit technology for the electrical isolation of device active regions. With the high integration of semiconductor devices, improper electrical isolation among devices increasingly leads to current leakage, for example junction leakage, consuming a significant amount of power as well as compromising device functionality. Among some examples of reduced functionality caused by improper electric isolation include latch-up, which can damage the circuit temporarily, or permanently, noise margin degradation, voltage threshold shift and cross-talk.
Shallow trench isolation (STI) is a preferred electrical isolation technique particularly for a semiconductor chip with high integration. The formation of STI structures generally involves filling trenches etched into a semiconducting substrate, for example silicon, with a chemical vapor deposition (CVD) silicon oxide (SiO2) which is then planarized by a chemical mechanical polishing (CMP) process which stops on a layer of silicon nitride (e.g., Si3N4) to yield a planar surface.
Shallow trench isolation features with trenches having submicrometer dimensions are effective in preventing latch-up and punch-through phenomena. Broadly speaking, conventional methods of producing a shallow trench isolation feature include: forming a hard mask of silicon nitride, also referred to as a pad nitride, overlying a pad oxide which in turn overlies the silicon substrate. The pad nitride is then patterned by a photolithographic process and etched to form a hard mask defining a trench feature. A trench is then etched into the silicon substrate to form a shallow trench isolation structure. Subsequently, the shallow trench isolation feature is back-filled, with a dielectric material, for example a CVD silicon dioxide, also referred to as STI oxide, followed by CMP planarization to remove excess STI oxide above the silicon nitride (hardmask) level. Subsequently, the silicon nitride hardmask layer is removed according to a wet etching process using hot phosphoric acid (H3PO4).
Residual stresses in STI structures caused by backfilling with STI oxide has become a problem as device sizes have decreased, frequently contributing to reduced charge carrier mobility in adjacent active regions. Prior art methods have proposed depositing nitride layers by CVD processes to counteract the stresses formed by the STI oxide and to act as an oxygen diffusion barrier.
One problem with prior art STI formation processes including CVD nitride liners deposited to line the STI trench is that the pad nitride and pad oxide layers must be removed by a wet etching process following STI oxide backfill and planarization steps. Typically wet etching processes include using phosphoric acid (H3PO4) to remove the pad nitride layer and HF hydrofluoric acid, hereinafter referred to as HF, to remove the underlying pad oxide layer.
A problem with etching both the pad nitride layer and the pad oxide layer is that the H3PO4 attacks the CVD nitride liner in the pad nitride etching process forming a divot at the STI trench edges and HF etching solution further attacks the STI oxide and an oxide liner, if present, along the STI trench edges thereby further widening the divot formed in the pad nitride etching process. As a result, etching divots are formed at the trench edges (corners) where high electrical fields are present during device operation causing device degradation including junction leakage and reverse short channel effects. Another drawback in the formation of divots at the STI trench edges is that the divot will act as a collector of residual polysilicon and/or metals in subsequent processes thereby increasing the likelihood of electrical shorting.
There is therefore a need in the semiconductor processing art to develop an improved STI formation process to avoid the formation of etching divots at STI trench edges to improve device performance and reliability.
It is therefore an object of the invention to provide an improved STI formation process to avoid the formation of etching divots at STI trench edges to improve device performance and reliability in addition to overcoming other shortcomings in the prior art.